In digital electronic circuitry, it is common to transfer data from one clock domain to another. Data is clocked out of a register by the first domain clock, and clocked into a register by the second domain clock. Generally, the two clocks are synchronous. That is, their phase relationship is constant. In such instances, the major problem in ensuring proper data transfer from one domain to the other is ensuring that the phase relationship is within a range that allows the data to meet setup and hold timing requirements.
Persons involved in the design and manufacture of integrated circuits (ICs), especially application-specific ICs (ASIC), desire to verify that data can be properly transferred between two clock domains in the IC die. For example, in many ASICs, data is transferred between “core” logic in one region of the IC die and input/output (I/O) logic in another region of the IC die. The I/O logic can include, for example, a Serializer/De-serializer or “SerDes.” In the prior art, proper data transfer between core logic and a SerDes has been verified in tests by transferring large amounts of test data between the core logic and SerDes and comparing the input data with the output data. Although this method can indicate that the ASIC is generally operational for its intended purpose, it does not necessarily prove that the ASIC has been designed and manufactured in a manner that meets clock phase specifications, since it is possible for a data transfer to be successful despite the two clocks having a phase relationship somewhat outside of the designed-for, i.e., specified, range.